The present disclosure relates to semiconductor integrated circuits, and more particularly to a technology of operating, at high speed, comparators as well as memory elements, associative memories, etc. incorporating comparators.
In a virtual memory system of an electronic computer, a translation look-aside buffer (TLB) is widely used as a means for speeding up address translation. The circuits of the TLB are generally comprised of a VPN memory array where virtual page numbers (hereinafter referred to as VPNs) are stored and a PPN memory array where physical page numbers (hereinafter referred to as PPNs) are stored. In address translation, the VPN memory array is searched for a desired VPN, and, once the matching VPN is found, the corresponding PPN is read from the PPN memory array.
In a general virtual memory system, the page size is variable to effectively use the memory space. In this case, since the effective bit count of a VPN stored in the TLB varies with the page size, a specific bit will be excluded from the search target.
In Japanese Unexamined Patent Publication No. H10-340589 (Patent Document 1) discloses a technology of changing the bit count of an address to be translated depending on the page size supported. More specifically, the semiconductor integrated circuit in Patent Document 1 arranges detection signal lines in a hierarchical manner: comparison results from content-addressable memory (CAM) cells are connected to local detection lines via transistors, and the local detection lines are connected to a common detection line via transistors controlled by data in size bits.